1. Field of the Invention
The present invention relates generally to a nonvolatile memory having a trap layer for trapping electric charge, and more particularly to a nonvolatile memory with various characteristics improved.
2. Description of the Related Art
There are two types in the flash memory, which is one of semiconductor nonvolatile memories, one type having a conductive floating gate enclosed within an oxide film between a control gate and a semiconductor substrate, and the other type, where an oxide film, a nitride film and an oxide film are formed between the control gate and the semiconductor substrate, and the nitride film, that is an insulating film, functions as a trap layer. Of the above-described two types, the latter stores the data 0 and 1, allowing the trap layer formed of the insulating film (or a trap gate) to trap electric charge for changing the threshold value of a cell transistor. As the trap layer is of insulating properties, electric charge cannot move through the interior of the trap layer. Therefore, the trap layer can accumulate electric charge in its both ends, so that two bits information can be stored.
FIG. 1 is a sectional view of a nonvolatile memory cell having a trap layer. On the surface of a P-type semiconductor substrate SUB, a first and a second source/drain areas SD1 and SD2 of N-type are provided, and on a channel area sandwiched between the SD1 and SD2, a silicon oxide film OX1, a silicone nitride film TRP, a silicon oxide film OX2, and a conductive control gate CG are formed in that order. The silicone nitride film OX2 can, as the trap layer, accumulate electric charge in the areas in its both ends, respectively (noted by black circles). One of the first and second source/drain areas SD1 and SD2 functions as a source, and the other functions as a drain or one functions as a drain, and the other functions as a source, depending on operations.
FIG. 2 is a diagram showing operations of a nonvolatile memory cell having a trap layer. During writing operation, the trap layer is allowed to trap a hot electron generated in the channel, after, for example, 9V is applied to the control gate, for example, 5V is applied to the first source/drain SD1, and further, for example, 0V is applied to the second source/drain SD2 and the substrate, respectively. By the injection of the channel hot electron, an electron is injected into the right-hand end of the trap layer. During erasing operation, for example, −6V is applied to the control gate, and for example, 6V is applied to the first source/drain SD1, respectively, and further the second source/drain SD2 is brought into a floating state, such that holes generated in the tunnel current between bands and flowing into the substrate from the first source/drain SD1 are injected into the trap layer. By this injection, the holes are neutralized with the electron trapped in the trap layer, and any electron no longer remains within the trap layer. In the erasing operation, the first and the second source/drains may the same potential (6V). In this case, the holes generated from both sides is injected into the trap layer.
During read-out operation, the voltage in the opposite direction to the direction employed during the writing operation is applied between the first and the second source/drains. This is a so-called reverse read. 0V and 5V for example are applied to the first source/drain SD1 and to the second source/drain SD2, respectively, and further, for example, 5V is applied to the control gate. At this time, if the electron is trapped at the right-hand end of the trap layer, the channel would not be formed, and the drain current would not flow, however, if any electron is not trapped at the side, the channel is formed and the drain current flows. Thus, the data can be read out.
If the trap layer accumulates electrons at its left-hand end, the relation between the first and the second source/drains SD1 and SD2 shown in FIG. 2 is reversed.
As described above, in nonvolatile memory having an insulating trap layer, as the memory cell can accumulate the data of 2 bits, it is expected that this memory cell can be used as a multi-bit memory cell. On the other hand, the cell structure having an insulating trap layer has a merit that its manufacturing process can be simpler, compared to the cell structure having a conductive floating gate.
Now, it has been proposed that, in nonvolatile memory having an insulating trap layer, only one end of the trap layer to be used as an accumulation area of electrons, and also as a 1 bit storing memory cell.
In this proposal, only one side of the trap layer is used for a data accumulation area, such that the opposite side of the trap layer is always kept in the erase state. The reason is as follows. If electrons are injected into the area on the opposite side, which is not used as memory, the threshold voltage of the cell transistor increases, thus causes the problem of increasing the read-out voltage in reading-out data on the side, which is to be used as memory. Furthermore, in order to inject an electron into the area on the opposite side which is not used as memory, writing (program) operation for that purpose is required, thereby causing another problem of complicating the data rewriting operation.
FIG. 3 is a flow chart of erasing operations of the conventional memory according to the above-described proposal. In FIG. 3, black circles indicate trapped state of the electrons of the cell transistor at each step, as well as a flow chart. Here, the right-hand end of the trap layer is the bit to be used as memory, and the left-hand end is the bit that is not used.
At the erasing start point S1, the electrons are not trapped, or are trapped on the right-hand end of the trap layer. Therefore, in erasing operation, first of all, pre-erase writing process is performed (S2). This process injects electrons into both ends of the trap layer. Then, erasing process S3 as shown in FIG. 2 is performed, and the holes are injected into both ends of the trap layer, and both of the use bit side and non-use bit side are brought, into the erased state. Through writing operation performed after that, an electron is injected into the use bit side.
As described above, in nonvolatile memory having a trap layer of the conventional 1 bit storing type, the non-use bit side is always kept in the erased state, and the non-use bit side is put in the erased state, even when a series of erasing operations have ended.
However, the inventors of the present invention have found that there is the following problem, when a nonvolatile memory cell having a trap layer is used as a 1-bit storage. FIG. 4 is a diagram showing the relation between the writing time and the threshold voltage Vth. In nonvolatile memory in which electric charge is stored in the trap layer for storing data, the threshold voltage of the non-use bit on the opposite side considerably affects the threshold voltage of the use bit. Therefore, the threshold voltage of the use bit varies depending on the state, whether it is the (written state), where an electron is trapped in the non-use bit on the opposite side, or (erased state), where an electron is not trapped. In short, the threshold voltage becomes higher when the non-use bit on the opposite side is in the written state.
With the increase in the threshold voltage, the writing time of the use bit is affected. As shown in FIG. 4, at the writing start point, the threshold voltage when the bit on the opposite side is in the written state WR is higher than the threshold voltage in the erased state ER, and also, the time required for reaching a specified threshold voltage Vt1 is faster when the bit on the opposite side is in the written state WR, compared to the erased state ER. Therefore, if the bit on the opposite side is in the written state, the writing time of the use bit can be shortened.
FIG. 5 is a diagram showing the relation between the data holding time and the threshold voltage Vth. This figure shows that, when the data holding time is zero, that means immediately after writing, a threshold voltage is the predetermined voltage Vt1, however, as the data holding time is lasting longer, the threshold voltage drops largely, if the bit on the opposite side is in the erased state ER; on the other hand, the threshold voltage drops slightly, if the bit on the opposite side is in the written state WR. This means that if electrons are accumulated on the bit on the opposite side too, the ratio of dropping of the threshold voltage of the use bit side, caused by the electrons accumulated on the use bit being extracted, is lower than when the electrons are not accumulated on the bit on the opposite side.
In addition, FIG. 6 is a diagram showing the relation between the rewriting number of times and the amount of charge loss. This figure shows that with the increase in the rewriting number of times, the reducing amount of the charge (electron) within the trap layer increases. That is because of deterioration caused by the increase in the electric field stress applying number of times to the first oxide film OX1 (see FIG. 1), along with the increase in the rewriting number of times.